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HMC5843
MD1
0
0
1
1
MD0
0
1
0
1
Mode
Continuous-Conversion Mode. In continuous-conversion mode, the
device continuously performs conversions an places the result in the
data register. RDY goes high when new data is placed in all three
registers. After a power-on or a write to the mode or configuration
register, the first measurement set is available from all three data
output registers after a period of 2/f DO and subsequent
measurements are available at a frequency of f DO , where f DO is the
frequency of data output.
Single-Conversion Mode. When single-conversion mode is selected,
device performs a single measurement, sets RDY high and returned
to sleep mode. Mode register returns to sleep mode bit values. The
measurement remains in the data output register and RDY remains
high until the data output register is read or another conversion is
performed.
Idle Mode. Device is placed in idle mode.
Sleep Mode. Device is placed in sleep mode.
Table 13: Operating Modes
Data Output X Registers A and B
The data output X registers are two 8-bit registers, data output register A and data output register B. These registers
store the measurement result from channel X. Data output X register A contains the MSB from the measurement result,
and data output X register B contains the LSB from the measurement result. The value stored in these two registers is a
16- bit value in 2’s complement form, whose range is 0xF800 to 0x07FF. DXRA0 t hrough DXRA7 and DXRB0 through
DXRB7 indicate bit locations, with DXRA and DXRB denoting the bits that are in the data output X registers. DXRA7 and
DXRB7 denote the first bit of the data stream. The number in parenthesis indicates the default value of that bit.
In the event the ADC reading overflows or underflows for the given channel, or if there is a math overflow during the bias
measurement, this data register will contain the value - 4096 in 2’s complement form. This register value will clear when
after the next valid measurement is made.
DXRA7
(0)
DXRB7
(0)
DXRA6
(0)
DXRB6
(0)
DXRA5
(0)
DXRB5
(0)
DXRA4
(0)
DXRB4
(0)
DXRA3
(0)
DXRB3
(0)
DXRA2
(0)
DXRB2
(0)
DXRA1
(0)
DXRB1
(0)
DXRA0
(0)
DXRB0
(0)
Table 14: Data Output X Registers A and B
Data Output Y Registers A and B
The data output Y registers are two 8-bit registers, data output register A and data output register B. These registers
store the measurement result from channel Y. Data output Y register A contains the MSB from the measurement result,
and data output Y register B contains the LSB from the measurement result. The value stored in these two registers is a
16- bit value in 2’s complement form, whose range is 0xF800 to 0x07FF. DYRA0 through DYRA7 and DYRB0 through
DYRB7 indicate bit locations, with DYRA and DYRB denoting the bits that are in the data output Y registers. DYRA7 and
DYRB7 denote the first bit of the data stream. The number in parenthesis indicates the default value of that bit.
In the event the ADC reading overflows or underflows for the given channel, or if there is a math overflow during the bias
measurement, this data register will contain the value - 4096 in 2’s complement form. This register value will clear when
after the next valid measurement is made.
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